Functional Description
Question 1
When the USB on the HT46RB50 is reset is the MCU also reset?
Answer
The 7th bit in the USC control register can be used to decide if a USB reset signal will also reset the MCU. When the bit is equal to 1, then a USB reset signal will also reset the MCU. If the bit is equal to 0, then a USB reset signal will not reset the MCU
Question 2
When a USB interrupt is generated on the HT46R50, how can it be determined which endpoint has been accessed?
Answer
When a USB interrupt occurs, the related USB register related endpoint access flag, EPXIF, will be set high. Note that X denotes the endpoint number,. By reading the USR register the accessed endpoint can be determined.
Question 3
How does the HT46RB50 enter the Suspend Mode and in this mode how much current is consumed?
Answer
If, when connected, there is no signal for 3ms, the HT46RB50 will enter the Suspend Mode. In this mode the third bit of the UCC register, USBCKEN, will be cleared and the USB clock stopped. Here the current consumption will be around 400μA.
Question 4
In the HT46RB50 how can the required operational FIFO?
Answer
By using the lowest three bits in the UCC register (EPS0~EPS2), it is possible to selected the indicated FIFO to implement operations. The following illustrates the relationship:
If EPS0~EPS2 is setup as “000” then endpoint 0 FIFI is selected
If EPS0~EPS2 is setup as “001” then endpoint 1 FIFI is selected
If EPS0~EPS2 is setup as “010” then endpoint 2 FIFI is selected
If EPS0~EPS2 is setup as “011” then endpoint 3 FIFI is selected
Question 5
How is data written to the FIFO?
Answer
1. Setup the FIFO, setup in the write mode (MISC TX bit = 1), setup the REQ bit = 1.
2. Check that the ready bit is = 1
3. Use the FIFO pointer register to write. At the same time record the amount of already read data.
4. Repeat steps 2 and 3 until the ready bit is equal to 0, which means that the FIFO data has all been written.
5. Set the MISC TX bit = 0
6. Clear the REQ bit to 0 to complete the write operation.
Question 6
How is the FIFO data read?
Answer
1. Select a FIFO group, setup in the read mode (MISC TX bit = 0), setup the REQ bit as 1.
2. Check the Ready bit value is = 1.
3. By using the FIFO pointer register, read the FIFO data. At the same time record the amount of already read data.
4. Repeat steps 2 and 3 until the ready bit is equal to 0, which means that the FIFO data has been fully read.
5. Set MISC TX bit = 1.
6. Clear the REQ bit to 0 to complete the read operation.
Question 7
When the HT46RB50 is used as a USB device, why is it necessary to connect a 1.5K pull-high resistor between the UDP (D+) pin and V330?
Answer
Because the HT46RB50, when used as a USB device, is in the full speed mode, this mode requires that the USB equipment data line D+ is connected to a pull-high resistor which is in turn connected to a 3.3V voltage level. For this reason a 1.5K pull-high resistor is connected between the UDP pin (D+) and V330.
Question 8
What are the operating steps for HT46RB50 serial interface transmit mode
?
Answer
Step 1: Select CKS and M1,M0 = 00, 01, 10
Step 2: Select CSEN, MLS (Same as Slave Mode)
Step 3: Set SBEN
Step 4: Write data to the SBDR register → Data stored in the TXRX register → Output CLK signal → Goto Step 5 → (SIO internal control→ Data Memory is in the TXRX buffer, SDI received data moved to the TXRX register → when data transmission has ended, the TXRX buffer will be written to the SBDR register
Step 5: Check WCOL: WCOL = 1 → clear WCOL and jump to Step 4; WCOL = 0 → jump to Step 6
Step6: Check TRF or wait for SBI (Serial Interface Interrupt)
Step7: Get data from the SBDR register
Step8: Clear TRF
Step9: Jump to Step 4
Question 9
What are the operating steps for the slave mode serial port on the HT46RB50?
Answer
1. Setup M1, M2 as “11”
2. Select CSEN, MLS – Same Master Mode
3. Set SBEN
4. Write data to the SBDR register → store data in TXRX register → wait for main controller clock (and SCS): CLK → jump to step 5 → (SIO internal control → CLK(SCS) receive → output data to TXRX register, SDI received data moded to TXRX buffer → after data transmission ended, TXRX buffer data placed into SBDR register)
5. Check that WCOL:WCOL = 1 → Clear WCOL and jump to Step 4, WCOL = 0 → Jump to Step 6
6. Check TRF or wait for SBI (Serial Interface Interrupt)
7. Obtain data from the SBDR register
8. Clear TRF
Question 10
How is a NAK packet generated for the USB Host?
Answer
After entering the USB interrupt, do not implement any operation, but directly leave the interrupt. Here the MCU will automatically return the USB host with a NAK packet.
Question 11
After the USB host has been suspended, how can the HT46RB50 wake up the host?
Answer
If the HT46RB50 is to wake up the host, when listing the USB configuration, in the configuration descriptor, it is necessary to open the remotewakeup function. After the USB host is suspended, when the HT46RB50 detects a wake-up signal, then the USB host can be woken up via the RMWK (USC first bit). After the USB host receives this it will transmit a resume signal to the HT46RB50.
Question 12
What is the purpose of bit 7 (LEN0) in the MISC register?
Answer
This bit shows the FIFO read data LEN0 handshake signal. When the host transmits zero length handshake data to the MCU, the MISC register bit LEN0 will be set to 1. However this bit will not be automatically cleared and the programmer must clear this bit to zero.
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